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XE1203F
4
GENERAL DESCRIPTION
The XE1203F is a direct conversion (Zero-IF) half-duplex data transceiver. The circuit operates in three different
ISM frequency bands (433 MHz, 868 MHz and 915 MHz) and uses 2-level FSK modulation/demodulation to
provide a complete transmission link. It is capable of operating at data rates between 1.2 and 152.3 kbit/s, making
it ideally suited for applications where high data rates are required. It also supports the Konnex standard where the
bit rate is 32.7 kbit/s. The device includes dedicated Barker encoder/decoder hardware that may be activated to
modulate/demodulate the transmitted signal to reduce in-band interferences.
The XE1203F is a highly programmable device – channel, bit rate, frequency deviation, output power, base band
filter bandwidth, sensitivity vs. linearity, RSSI feature, and many other parameters – which makes it extremely
flexible, to meet a large number of end user requirements.
The main functional blocks of the XE1203F are the receiver, the transmitter, the frequency synthesizer and some
service blocks. The device also includes a series of configuration and status registers. In a typical application, the
XE1203F is programmed by a microcontroller via the 3-wire serial bus SI, SO, SCK to write to and read from these
registers.
The Receiver converts the incoming 2-level FSK modulated signal into a synchronized bit stream.
The Transmitter performs the modulation of the carrier by an input bit stream and the transmission of the
modulated signal.
The Frequency Synthesizer generates the local oscillator (LO) signal for the receiver section as well as the
continuous phase FSK modulated signal for the transmitter section.
The Service Blocks provide the internal voltage and current sources and provide all the necessary functions for
the circuit to work properly.
The Configuration Registers are a set of variable-length registers that are used to store various settings to
operate the XE1203F transceiver circuit. They are listed below in Table 4. Refer to Section 5.2 for the detailed
descriptions of these registers. These registers are accessed in write or read mode through the 3-wire serial bus,
as described in Section 5.1.
Name
ConfigSwitch
RTParam
FSParam
SWParam
DataOut
ADParam
Pattern
Description
1-bit data to switch between 2 sets of user-predefined SWParam Configuration Registers
Receiver and transmitter parameters
LO, Bitrate, Deviation and other frequency parameters
2 sets of user-predefined configuration registers
Status register which can be read through the 3-wire serial interface
Additional parameters
Reference pattern for the “pattern recognition” feature
Table 4: Configuration Registers
Naming convention: throughout this document, each individual bit in a particular Configuration Register includes
the name of this register followed by a bit identifier. For example, RTParam_Band are the “Band” bits within the
RTParam register.
The Digital Interface provides internal control signals for the whole circuit according to the configuration register
settings.
4.1
THE RECEIVER SECTION
The receiver converts the incoming 2-level FSK modulated signal into a synchronized bit stream. The receiver is
composed of a low-noise amplifier, two down-conversion mixers, two base band filters, two base band amplifiers,
two limiters, a demodulator and a bit synchronizer. The bit synchronizer translates the output of the demodulator
into a glitch-free bit stream available on the pin DATA. It also generates a synchronized clock, DCLK, which can be
? Semtech 2008
7
www.semtech.com
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